True Random Number Generator - Analog Noise Source

​AIS 31 compliant
Fully integrated
Robust architecture
Analog-based source​
Low power consumption

Robust, fully-integrated, state-of-the-art physical entropy source
Differential jitter extraction through a PLL-based fully symmetric architecture
Stochastic model of the entropy source for AIS 31 certification
Asynchronous random clock signal output
Random stream synchronization through an external sampling clock
Typical characteristics of a 55 nm implementation:

• compliant with the AIS 31 standard (Method A, Procedure A) up to 100 kbit/s
• with optional digital post-processing: fully compliant with the AIS 31 (Method A & B)
  and NIST SP 800-90B standards up to 100 kbit/s
• startup time shorter than 80 µs
• power-supply voltage range: 1.2 V ±10%
• operating current smaller than 40 µA
• standby current lower than 1 µA
• operating junction temperature range: -40°C to 125°C
• silicon area smaller than 0.02 mm²

Silicon proven in 130 nm, 110 nm, 65 nm and 55 nm CMOS processes
Digital post-processing available separately

GDSII stream and layer map file
Library Exchange Format (LEF) file
Circuit Description Language (CDL) netlist
VHDL behavioral model
Liberty Timing File (.lib)
Design specification