Interfaces
SWP Slave Digital Controller
Overview
The Single Wire Protocol (SWP) Slave Digital Controller is a fully integrated protocol manager intended to interface the UICC (SWP slave) to the NFC chip (SWP master) through a single wire.
Specifications
Benefits
ETSI 102.613 compliant
Continuous bidirectional stream
Low gate count
Silicon proven
Straightforward integration
Features
Fully compliant with the ETSI 102.613 standard
Continuous bidirectional stream through eight physical buffers:
- four 32 bytes buffers for automatic frame emission
- four 32 bytes buffers for automatic frame reception
256 bytes Dual Port RAM acting as a physical buffer
Total gate count smaller than 2.3 kgates (excluding RAM)
Straightforward integration through an APB bus interface
silicon proven in a 130 nm CMOS process
Analog front end available separately
Master digital controller available separately
Deliverables
VHDL source codes
VHDL test benches
Standalone simulation patterns
Synopsys synthesis scripts
Design specification