Interfaces

ISO 7816-3 Analog Front End

Overview
The ISO 7816-3 Analog Front End (AFE) is a mixed-signal IP including five fully integrated I/O pads intended for both interface device (reader) and Integrated Circuit Card (ICC).

Specifications

Benefits

ISO 7816-3 compliant
Fully integrated
Silicon proven
Class A, B & C
Internal pull-up

Features

Five fully-integrated I/O pads: CLK, RST, I/O, VCC and GND
Fully compliant with the ISO/IEC 7816-3 standard (class A, B and C)
Silicon proven in 130 nm, 65 nm and 55 nm CMOS processes
Square pad with 80 µm x 80 µm opening
Operating junction temperature range: -40°C to 125°C
CLK digital input pad:

  • up to 50 MHz clock signal for high-speed test
  • internal pull-up with activation signal
  • input noise rejection through optional filter and Schmitt trigger buffer
  • standby mode canceling the current consumption
  • embedded level-shifters (Vcc level pad signal; Vdd level core control signals)
  • power-up protection
  • silicon area smaller than 0.016 mm² in a 130 nm CMOS process (156 µm x 101 µm)

RST digital input pad:

  • internal pull-up with activation signal
  • input noise rejection through Schmitt trigger buffer
  • standby mode canceling the current consumption
  • embedded level-shifters (Vcc level pad signal; Vdd level core control signals)
  • power-up protection
  • silicon area smaller than 0.016 mm² in a 130 nm CMOS process (156 µm x 101 µm)

I/O bidirectional digital pad:

  • three output modes with optional slew-rate control: Slow ISO, Fast ISO and CMOS
  • internal pull-up with activation signal
  • input noise rejection through Schmitt trigger buffer
  • standby mode canceling the current consumption
  • embedded level-shifters (Vcc level pad signal; Vdd level core control signals)
  • power-up protection
  • independent control of the reception and transmission paths
  • silicon area smaller than 0.024 mm² in a 130 nm CMOS process (231 µm x 101 µm)

VCC power supply pad:

  • silicon area smaller than 0.010 mm² in a 130 nm CMOS process (97 µm x 101 µm)

GND power supply pad:

  • silicon area smaller than 0.010 mm² in a 130 nm CMOS process (97 µm x 101 µm)

ESD protection and digital controller available separately

Deliverables

GDSII stream and layer map file
Library Exchange Format (LEF) file
Circuit Description Language (CDL) netlist
Liberty Timing File (.lib)
VHDL behavioral model
Design specification