Active Shield
Specifications
Benefits
Tamper-resistant
Dynamic detection
Configurable architecture
Adjustable parameters
Silicon proven
Features
Fully integrated countermeasure against cut and strap attacks
Dynamic detection of tampering attempts
Shield characteristics adjustable through a graphical user interface:
- security level
- mesh number and density
- gate number
- power consumption
- via distribution
- routing congestion
Easy integration in typical design flows through RTL files and back-end scripts
Fully compatible with both Cadence SoC Encounter and Synopsys IC Compiler
Silicon proven in 110 nm, 90 nm, 65 nm and 55 nm CMOS processes
Typical power consumption: 5 µW to protect a 2 mm² area in a 65 nm CMOS process
Typical silicon area overhead lower than 3%
Straightforward integration through AMBA APB bus (customized on request)
Deliverables
VHDL source codes
VHDL test benches
Synopsys synthesis scripts
Design specification