Cryptography

AES Coprocessor

Overview
The AES Coprocessor encrypts and decrypts 128-bit data blocks by computing an AES algorithm with a 128, 192 or 256-bit key through a highly secure architecture.

Specifications

Benefits

Secure implementation
Key expander included
Configurable ar​chitecture
Hardened against SCA
Silicon proven​

Features

Decryption and encryption
Key expander included
128-bit data blocks
128, 196 and 256-bit keys
Supported modes: ECB, CBC, CFB, OFB, CTR, XTS, GCM, EAX and CCM
Configurable architecture:

  • encryption and decryption; encryption only; decryption only
  • hardware datapath size: 32, 64 or 128-bits
  • optional fault-injection countermeasures
  • optional DMA support

High performances:

  • 11 cycles for the fastest architecture
  • 19 kgates for the smallest architecture
  • more than 1 GHz in a 65 nm LVT process

  • State-of-the-art countermeasures against SPA, DPA and fault injection attacks
    AMBA APB bus interface (AHB with the optional DMA)
    C low-level API

Deliverables

VHDL source codes
C non-regression tests
C low-level API
Code coverage, linker and synthesis reports
Design specification